LTC4268IDKD-1#PBF【PDF 11/46 页】IC PD HIGH POWER W/CNTRL 32-DFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录42

7页 8页 9页 10页 [11页]12页 13页 14页 15页

42681fc

LTC4268-1

pin FuncTions

ance of the upper divider resistor. The user can control

the amount of hysteresis by adjusting the impedance of

the divider. Tie the UVLO pin to V

if you are not using

this function. See the Applications Information for details.

This pin is used for the UVLO function of the switching

regulator. The PD interface section has an UVLO defined

by the IEEE 802.3af specification.

SENSE, SENSE+ (Pins 19, 20): Current Sense Inputs.

These pins are used to measure primary side switch cur-

rent through an external sense resistor. Peak primary side

current is used in the converter control loop. Make Kelvin

connections to the sense resistor R

SENSE

to reduce noise

problems. SENSE connects to the GND side. At maximum

current (V

CMP

at its maximum voltage) SENSE pins have

100mV threshold. The signal is blanked (ignored) during

the minimum turn-on time.

CMP

(Pin 21): Load Compensation Capacitive Control.

Connect a capacitor from C

CMP

to GND in order to reduce

the effects of parasitic resistances in the feedback sensing

path. A 0.1礔 ceramic capacitor suffices for most applica-

tions. Short this pin to GND in less demanding applications.

CMP

(Pin 22): Load Compensation Resistive Control.

Connect a resistor from R

CMP

to GND in order to com-

pensate for parasitic resistances in the feedback sensing

path. In less demanding applications, this resistor is not

needed and this pin can be left open. See Applications

Information for details.

PGDLY (Pin 23): Primary Gate Delay Control. Connect an

external programming resistor (R

PGDLY

) to set delay from

synchronous gate turn-off to primary gate turn-on. See

Applications Information for details.

PG (Pin 24): Primary Gate Drive. PG is the gate drive pin

for the primary side MOSFET Switch. Large dynamic cur-

rents flow during voltage transitions. See the Applications

Information for details.

NC (Pin 25): No Internal Connection.

NEG

(Pins 26, 27, 28): System Negative Rail. Tie to the

GND pin to supply power to the flyback controller through

the internal power MOSFET. V

NEG

is high impedance until

the input voltage rises above the UVLO turn-on threshold.

The output is then connected to V

PORTN

through a current-

limited internal MOSFET switch. Pins 26, 27 and 28 must

be electrically tied together.

PWRGD (Pin 29): Active High Power Good Output,

Open-Collector. Signals to the flyback controller that the

LTC4268-1 MOSFET is on and that the flyback controller

can start operation. High impedance indicates power is

good. PWRGD is referenced to V

NEG

and is low imped-

ance during inrush and in the event of a thermal overload.

PWRGD is clamped to 14V above V

NEG

PWRGD (Pin 30): Active Low Power Good Output, Open-

Drain. Signals to the DC/DC converter that the LTC4268-1

MOSFET is on and that the converter can start operation.

Low impedance indicates power is good. PWRGD is ref-

erenced to V

PORTN

and is high impedance during detec-

tion, classification and in the event of a thermal overload.

PWRGD has no internal clamps.

NC (Pin 31): No Internal Connection.

PORTP

(Pin 32): Positive Power Input. Tie to the input

port power return through the input diode bridge.

GND (Pin 33): Ground. This is the negative rail connec-

tion for both signal ground and gate driver grounds. This

pin should be connected to V

NEG

. Careful attention must

be paid to layout. See the Applications Information for

details.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式